Search - verilog ip

[VHDL-FPGA-Verilog] RAM_InterWave

Description: RAM 通过ip核的生成使用verilog 的编写的，可以拿来直接进行例化使用。-RAM generated by using verilog ip core prepared, can be used directly instantiated using.
Platform: | Size: 2048 | Author: 于健 | Hits:

[VHDL-FPGA-Verilog] DES_Triple-DES-IP-Cores

Description: Triple DES 密码算法。利用Xillinx公司的Virtex-II芯片测试了。正常动作。-Triple DES core implementation in verilog. It takes three standard 56 bit keys and 64 bits of data as input and generates a 64 bit encrypted/decrypted result.
Platform: | Size: 70656 | Author: 金铁男 | Hits:

[Other] IPcore

Description: verilog IP核调用子程序，源码-Verilog IP core call subroutine, the source code
Platform: | Size: 2058240 | Author: qiqi | Hits:

[VHDL-FPGA-Verilog] i2c-master

Description: i2c 总线 host 控制器， fpga上验证过，可以实现i2c 通信。-verilog IP for i2c master controller
Platform: | Size: 978944 | Author: guoqingsheng | Hits:

[VHDL-FPGA-Verilog] Altera FFT IP核使用实例

Description: Verilog，关于如何调用Altera官方的FFT iP核，如何输入和得到输出的实例。
Platform: | Size: 9807 | Author: dumn1234 | Hits:

[USB develop] USB-IPcore-Verilog

Description: USB IP 核设计，Verilog，ISE工程可以打开-USB IP core design, Verilog, ISE project can be opened
Platform: | Size: 5345280 | Author: 赵海峰 | Hits:

[Software Engineering] 8pic_MCU

Description: 8位MCUIP核的设计与应用（verilog IP核设计）PIC处理器西安电子科技大学硬件工程师培训资料-Design and Application of 8 MCU IP cores (verilog IP core design) PIC processor Xi an University of Electronic Science and Technology Hardware Engineer training materials
Platform: | Size: 11117568 | Author: 崔琦 | Hits:

[VHDL-FPGA-Verilog] Verilog-IIC-read-MPU6050-Filter

Description: 本代码实现了读MPU6050 三轴6个数据，用其中的GY和AZ、AX结合融合滤波算法，解出X单轴角度，并在黑金开发板的EP4C15F17C8芯片上调试成功，±5°范围内LED灯灭，左右摆动时相应左右灯亮。顶层模块每隔5ms，发出一个is_read高电平，下面的模块读取一次数据，并计算，更新LED状态。有关计算都用的ip核，占用资源很大。希望对小小小小白有所帮助。 -Verilog codes read 6 axis data of MPU6050, and use GY AZ AX with complementary filtering arithmetic to calculate X axis angle. Codes run at Altera Chip EP4C15F17C8 and set 2 led light if X angle beyond ±5°. Zip includes .v and .doc.
Platform: | Size: 9501696 | Author: 魏溢 | Hits:

[Other Embeded program] Altera-LVDS_IP

Description: 自己总结的Altera_LVDS的IP核的设计及仿真分析，已在实际工程中应用到，并且带有源代码和仿真代码，总结的文档，非常有用。(My summary of the Altera_LVDS IP kernel design and simulation analysis, has been applied in practical engineering, and with source code and simulation code, summary of the document, very useful.)
Platform: | Size: 3191808 | Author: 何河 | Hits:

[Other] lvds

Description: XILINX 官方的LVDS IP核，亲测可用。。。。。(XILINX official LVDS IP kernel, pro test available.....)
Platform: | Size: 282624 | Author: shanyuan001 | Hits:

[MPI] MY 80c51 IP

Description: verilog和vhdl混写的工程内含mc8051软核及最小系统经测试已调通(Verilog and VHDL mixed with the project, including the mc8051 soft core and the smallest system, the test has been transferred)
Platform: | Size: 16939008 | Author: 嘿哟 | Hits:

[VHDL-FPGA-Verilog] ddr3_rw_ctrl

Description: verilog基于DDR3 xilinx IP核的DDR3的读写控制，方便学习(it is based on DDR3 IP core of xilinx)
Platform: | Size: 1024 | Author: superali | Hits:

[Embeded-SCM Develop] SPI

Description: SPI（Serial Peripheral Interface，串行外设接口）是Motorola公司提出的一种同步串行数据传输标准，是一种高速的，全双工，同步的通信总线，在很多器件中被广泛应用。 SPI相关缩写 SS: Slave Select，选中从设备，片选。 CKPOL (Clock Polarity) = CPOL = POL = Polarity = （时钟）极性 CKPHA (Clock Phase) = CPHA = PHA = Phase = （时钟）相位 SCK = SCLK = SCL = SPI的时钟（Serial Clock） Edge = 边沿，即时钟电平变化的时刻，即上升沿(rising edge)或者下降沿(falling edge)。对于一个时钟周期内，有两个edge，分别称为： Leading edge = 前一个边沿 = 第一个边沿，对于开始电压是1，那么就是1变成0的时候，对于开始电压是0，那么就是0变成1的时候； Trailing edge = 后一个边沿 = 第二个边沿，对于开始电压是1，那么就是0变成1的时候（即在第一次1变成0之后，才可能有后面的0变成1），对于开始电压是0，那么就是1变成0的时候；(SPI (Serial Peripheral Interface, serial peripheral interface) is a synchronous serial data transmission standard put forward by Motorola company, is a high-speed, full duplex, synchronous communication bus, is widely used in many devices. SPI related abbreviations SS: Slave Select, selected from the device, chip select. CKPOL (Clock, Polarity) = CPOL = POL = Polarity = (clock) polarity CKPHA (Clock, Phase) = CPHA = PHA = Phase = (clock) phase SCK = SCLK = SCL = SPI clock (Serial, Clock) Edge = edge, instant clock, level change time, i.e. rising edge (rising, edge) or falling edge (falling, edge). For a clock cycle, there are two edge, respectively: Leading edge = front edge = first edge, for start voltage is 1, then 1 is 0, for start voltage is 0, then 0 is 1; Trailing = edge = second after an edge edge, the start voltage is 1, it is 0 to 1 of the time (that is, after the first 1 to 0, it may be behind the 0 to 1), the start voltage is 0, it is 1 to 0 times;)
Platform: | Size: 6144 | Author: helimpopo | Hits:

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[VHDL-FPGA-Verilog] RAM_InterWave

[VHDL-FPGA-Verilog] DES_Triple-DES-IP-Cores

[Other] IPcore

[VHDL-FPGA-Verilog] i2c-master

[VHDL-FPGA-Verilog] Altera FFT IP核使用实例

[USB develop] USB-IPcore-Verilog

[Software Engineering] 8pic_MCU

[VHDL-FPGA-Verilog] Verilog-IIC-read-MPU6050-Filter

[Other Embeded program] Altera-LVDS_IP

[Other] lvds

[MPI] MY 80c51 IP

[VHDL-FPGA-Verilog] ddr3_rw_ctrl

[Embeded-SCM Develop] SPI

[Communication-Mobile] CH04_GTP_TEST

[VHDL-FPGA-Verilog] hdl-2014_r2.tar

[VHDL-FPGA-Verilog] hdl-2014_r2

[VHDL-FPGA-Verilog] hdl-2015_r2.tar

[VHDL-FPGA-Verilog] hdl-2015_r2

[VHDL-FPGA-Verilog] hdl-2016_r2.tar

[VHDL-FPGA-Verilog] hdl-2016_r2

CodeBus www.codebus.net

Category

Source Code

Web/Internet

Develop Tools

Document

Other

Search in results

OS

Platform

Language

File Type

Search list

[VHDL-FPGA-Verilog] RAM_InterWave

[VHDL-FPGA-Verilog] DES_Triple-DES-IP-Cores

[Other] IPcore

[VHDL-FPGA-Verilog] i2c-master

[VHDL-FPGA-Verilog] Altera FFT IP核 使用实例

[USB develop] USB-IPcore-Verilog

[Software Engineering] 8pic_MCU

[VHDL-FPGA-Verilog] Verilog-IIC-read-MPU6050-Filter

[Other Embeded program] Altera-LVDS_IP

[Other] lvds

[MPI] MY 80c51 IP

[VHDL-FPGA-Verilog] ddr3_rw_ctrl

[Embeded-SCM Develop] SPI

[Communication-Mobile] CH04_GTP_TEST

[VHDL-FPGA-Verilog] hdl-2014_r2.tar

[VHDL-FPGA-Verilog] hdl-2014_r2

[VHDL-FPGA-Verilog] hdl-2015_r2.tar

[VHDL-FPGA-Verilog] hdl-2015_r2

[VHDL-FPGA-Verilog] hdl-2016_r2.tar

[VHDL-FPGA-Verilog] hdl-2016_r2

CodeBus www.codebus.net

[VHDL-FPGA-Verilog] Altera FFT IP核使用实例